VHDL Entity and Architecture Descriptions USF Computer. Generate statements are concurrent VHDL constructs that may. Vhdl generic if else. VHDL Language Reference TU Ilmenau. This statement directs the driver of Signal1 to generate a Value Time pair to. AR 9363 31i COREGEN VHDL Using VHDL GENERATE. The generate statement in VHDL can automatically duplicate a block of code to closures with identical signals processes and instances.